1. Technical Field
The present invention relates to an apparatus for lock detection used in a frequency synthesizer and a method thereof, and more particularly, to an apparatus for lock detection suitable for a fractional-N frequency synthesizer and method thereof.
2. Description of the Related Art
The following descriptions do not constitute the related art and only provide background information related to embodiments of the present invention.
A frequency synthesizer generates and sends signals at a desired frequency within a predetermined range. A frequency synthesizer is generally designed using a phase locked loop (hereinafter referred to as PLL).
Such a PLL-based frequency synthesizer divides an output frequency by N (N being a positive integer) and outputs a desired frequency by comparing the divided frequency with a reference frequency less vulnerable to surrounding environments such as temperature.
PLL-based frequency synthesizers are classified into integer-N frequency synthesizers and fractional-N frequency synthesizers according to whether N is fixed.
In the integer-N frequency synthesizer, N, i.e. an output frequency division factor, has a fixed value and thus a division ratio is an integer. On the contrary, in the Fractional-N frequency synthesizer, N changes into two or more values adjacent to N and thus frequency division is performed several times to achieve interpolation such that a division ratio becomes a real number.
At low frequencies, a desired output frequency can be obtained even when the integer-N frequency synthesizer is used. However, at high frequencies, since the integer-N frequency synthesizer has difficulty in fine adjustment of an output frequency, it is difficult to obtain a desired output frequency.
A noise level of a frequency synthesizer can be represented by 20 log N[dB]. Since a reference frequency Fref and an output frequency FVCO satisfy a relationship of ‘FVCO=F×N’, fine adjustment of the output frequency is possible even when the reference frequency is reduced. However, in this case, a value of N needs to be increased, and thus lots of noise occur based on the formula 20 log N[dB]. When a division ratio is a real number instead of an integer, fine adjustment of the output frequency is possible without reduction of the reference frequency, which is the primary benefit of the fractional-N frequency synthesizer. In addition, the fractional-N frequency synthesizer allows widened output frequency bandwidth and narrow channel spacing, thereby satisfying various communication standards.
The expression “frequency synthesizer is locked” means that a divided output frequency and a reference frequency are identical to each other and only have difference in phase. An output frequency derived from the frequency synthesizer is not applicable to various electronics, such as communication apparatuses or multimedia, until the frequency synthesizer is locked. Thus, the frequency synthesizer is provided with a lock detector configured to determine whether a current output frequency is locked.
Some examples of typical lock detectors are disclosed in KR Patent Publication No. 2001-0005039 A, KR Patent Publication No. 2006-0010032 A, and the like. Although these lock detectors are suitable for use in an integer-N frequency synthesizer with a fixed N value, there is a problem of inaccuracy in lock detection when used in a fractional-N frequency synthesizer with a variable N value.
Embodiments of the present invention provide a method and apparatus for lock detection used in a fractional-N frequency synthesizer, which can inform that an output frequency is locked to a desired frequency due to normal operation of a PLL in a rapid and accurate manner.